/* *****************************************************************************

  Copyright (C), 2001-2011, Huawei Tech. Co., Ltd.

 ******************************************************************************
  File Name     : hinic3_comm_cmd.h
  Version       : Initial Draft
  Created       : 2019/4/25
  Last Modified :
  Description   : NIC Commands between Driver and MPU
  Function List :
***************************************************************************** */

#ifndef HINIC3_NIC_CMD_H
#define HINIC3_NIC_CMD_H

/*
 * Commands between NIC to MPU
 */
enum hinic3_nic_cmd {
    HINIC3_NIC_CMD_VF_REGISTER = 0, /* only for PFD and VFD */

    /* FUNC CFG */
    HINIC3_NIC_CMD_SET_FUNC_TBL = 5,
    HINIC3_NIC_CMD_SET_VPORT_ENABLE,
    HINIC3_NIC_CMD_SET_RX_MODE,
    HINIC3_NIC_CMD_SQ_CI_ATTR_SET,
    HINIC3_NIC_CMD_GET_VPORT_STAT,
    HINIC3_NIC_CMD_CLEAN_VPORT_STAT,
    HINIC3_NIC_CMD_CLEAR_QP_RESOURCE,
    HINIC3_NIC_CMD_CFG_FLEX_QUEUE,
    /* LRO CFG */
    HINIC3_NIC_CMD_CFG_RX_LRO,
    HINIC3_NIC_CMD_CFG_LRO_TIMER,
    HINIC3_NIC_CMD_FEATURE_NEGO,

    /* MAC & VLAN CFG */
    HINIC3_NIC_CMD_GET_MAC = 20,
    HINIC3_NIC_CMD_SET_MAC,
    HINIC3_NIC_CMD_DEL_MAC,
    HINIC3_NIC_CMD_UPDATE_MAC,
    HINIC3_NIC_CMD_GET_ALL_DEFAULT_MAC,

    HINIC3_NIC_CMD_CFG_FUNC_VLAN,
    HINIC3_NIC_CMD_SET_VLAN_FILTER_EN,
    HINIC3_NIC_CMD_SET_RX_VLAN_OFFLOAD,
    HINIC3_NIC_CMD_SMAC_CHECK_STATE,

    /* SR-IOV */
    HINIC3_NIC_CMD_CFG_VF_VLAN = 40,
    HINIC3_NIC_CMD_SET_SPOOPCHK_STATE,
    /* RATE LIMIT */
    HINIC3_NIC_CMD_SET_MAX_MIN_RATE,

    /* RSS CFG */
    HINIC3_NIC_CMD_RSS_CFG = 60,
    HINIC3_NIC_CMD_RSS_TEMP_MGR, /* TODO: delete after implement nego cmd */
    HINIC3_NIC_CMD_GET_RSS_CTX_TBL, /* TODO: delete: move to ucode cmd */
    HINIC3_NIC_CMD_CFG_RSS_HASH_KEY,
    HINIC3_NIC_CMD_CFG_RSS_HASH_ENGINE,

    HINIC3_NIC_CMD_IPCS_ERR_RSS_ENABLE_OP = 66, /* IP checksum error packets, enable rss quadruple hash */

    /* DPI/FDIR */
    HINIC3_NIC_CMD_ADD_TC_FLOW = 80,
    HINIC3_NIC_CMD_DEL_TC_FLOW,
    HINIC3_NIC_CMD_GET_TC_FLOW,
    HINIC3_NIC_CMD_FLUSH_TCAM,
    HINIC3_NIC_CMD_CFG_TCAM_BLOCK,
    HINIC3_NIC_CMD_ENABLE_TCAM,
    HINIC3_NIC_CMD_GET_TCAM_BLOCK,
    HINIC3_NIC_CMD_CFG_DPI_TABLE_ID,
    HINIC3_NIC_CMD_SET_DPI_EN = 88,
    HINIC3_NIC_CMD_CFG_DPI_MODE,
    HINIC3_NIC_CMD_CFG_DPI_FLUSH,
    HINIC3_NIC_CMD_SET_FDIR_STATUS,
    HINIC3_NIC_CMD_GET_DPI_COUNTER,

    /* PORT CFG */
    HINIC3_NIC_CMD_SET_PORT_ENABLE = 100,
    HINIC3_NIC_CMD_CFG_PAUSE_INFO,

    HINIC3_NIC_CMD_SET_PORT_CAR,
    HINIC3_NIC_CMD_SET_ER_DROP_PKT,

    HINIC3_NIC_CMD_VF_COS,
    HINIC3_NIC_CMD_SETUP_COS_MAPPING,
    HINIC3_NIC_CMD_SET_ETS,
    HINIC3_NIC_CMD_SET_PFC,
    HINIC3_NIC_CMD_QOS_ETS,
    HINIC3_NIC_CMD_QOS_PFC,
    HINIC3_NIC_CMD_QOS_DCB_STATE,
    HINIC3_NIC_CMD_QOS_PORT_CFG,
    HINIC3_NIC_CMD_QOS_MAP_CFG,

    HINIC3_NIC_CMD_TX_PAUSE_EXCP_NOTICE = 118,
    HINIC3_NIC_CMD_INQUIRT_PAUSE_CFG = 119,

    /* MISC */
    HINIC3_NIC_CMD_BIOS_CFG = 120,
    HINIC3_NIC_CMD_SET_FIRMWARE_CUSTOM_PACKETS_MSG,

    /* BOND */
    HINIC3_NIC_CMD_BOND_DEV_CREATE = 134,
    HINIC3_NIC_CMD_BOND_DEV_DELETE,
    HINIC3_NIC_CMD_BOND_DEV_OPEN_CLOSE,
    HINIC3_NIC_CMD_BOND_INFO_GET,
    HINIC3_NIC_CMD_BOND_ACTIVE_INFO_GET,
    HINIC3_NIC_CMD_BOND_ACTIVE_NOTICE,

    /* DFX */
    HINIC3_NIC_CMD_GET_SM_TABLE = 140,
    HINIC3_NIC_CMD_RD_LINE_TBL,

    HINIC3_NIC_CMD_SET_UCAPTURE_OPT = 160, /* TODO: move to roce */
    HINIC3_NIC_CMD_SET_VHD_CFG,

    /* TODO: move to HILINK */
    HINIC3_NIC_CMD_GET_PORT_STAT = 200,
    HINIC3_NIC_CMD_CLEAN_PORT_STAT,
    HINIC3_NIC_CMD_CFG_LOOPBACK_MODE,
    HINIC3_NIC_CMD_GET_SFP_QSFP_INFO,
    HINIC3_NIC_CMD_SET_SFP_STATUS,
    HINIC3_NIC_CMD_GET_LIGHT_MODULE_ABS,
    HINIC3_NIC_CMD_GET_LINK_INFO,
    HINIC3_NIC_CMD_CFG_AN_TYPE,
    HINIC3_NIC_CMD_GET_PORT_INFO,
    HINIC3_NIC_CMD_SET_LINK_SETTINGS,
    HINIC3_NIC_CMD_ACTIVATE_BIOS_LINK_CFG,
    HINIC3_NIC_CMD_RESTORE_LINK_CFG,
    HINIC3_NIC_CMD_SET_LINK_FOLLOW,
    HINIC3_NIC_CMD_GET_LINK_STATE,
    HINIC3_NIC_CMD_LINK_STATUS_REPORT,
    HINIC3_NIC_CMD_CABLE_PLUG_EVENT,
    HINIC3_NIC_CMD_LINK_ERR_EVENT,
    HINIC3_NIC_CMD_SET_LED_STATUS,

    HINIC3_NIC_CMD_MAX = 256,
};

/* NIC CMDQ MODE */
enum hinic3_ucode_cmd {
    HINIC3_UCODE_CMD_MODIFY_QUEUE_CTX = 0,
    HINIC3_UCODE_CMD_CLEAN_QUEUE_CONTEXT,
    HINIC3_UCODE_CMD_ARM_SQ,
    HINIC3_UCODE_CMD_ARM_RQ,
    HINIC3_UCODE_CMD_SET_RSS_INDIR_TABLE,
    HINIC3_UCODE_CMD_SET_RSS_CONTEXT_TABLE,
    HINIC3_UCODE_CMD_GET_RSS_INDIR_TABLE,
    HINIC3_UCODE_CMD_GET_RSS_CONTEXT_TABLE,
    HINIC3_UCODE_CMD_SET_IQ_ENABLE,
    HINIC3_UCODE_CMD_SET_RQ_FLUSH = 10,
    HINIC3_UCODE_CMD_MODIFY_VLAN_CTX,
    HINIC3_UCODE_CMD_DPI_HASH_TABLE,
};

#endif /* HINIC3_NIC_CMD_H */
